1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. More particularly, the present invention relates to a magnetic random access memory (MRAM) including a middle oxide layer and an oxidation prevention layer. Further, the present invention relates to a method for providing such an MRAM, and may be a hetero-method.
2. Description of the Related Art
A magnetic random access memory (MRAM) is a memory device for reading and writing data using a phenomenon that resistance values of a magnetic tunneling junction (MTJ) layer change according to a magnetization direction of two magnetic layers forming the MTJ layer.
An MRAM may be highly integrated and can perform high-speed operations similar to a dynamic random access memory (DRAM) or a synchronous dynamic random access memory (SRAM). An MRAM also has a non-volatile characteristic so that data may be stored for a long time without requiring a refresh operation.
FIG. 1 illustrates a cross-section of a general structure of an MRAM. As illustrated in FIG. 1, an MRAM generally includes a transistor T performing a switching process and one MTJ layer S, which is electrically connected to the transistor T and where data such as “0” and “1” are written.
Referring to FIG. 1, in a conventional method of manufacturing an MRAM, a gate stacking material 12, which includes a gate electrode, is formed on a semiconductor substrate 10. Source and drain areas 14 and 16 are formed at both sides of the gate stacking material 12 in the semiconductor substrate 10. The gate stacking material 12 and the source and drain areas 14 and 16 together form the transistor T, which performs a switching process. In FIG. 1, reference numeral 11 indicates a field oxide layer. An interlayer insulating layer 18 covering the transistor T is formed on the semiconductor substrate 10. A data line 20, covered by the interlayer insulating layer 18, is then formed over and in parallel with the gate stacking material 12. A contact hole 22, exposing the drain area 16, is formed in the interlayer insulating layer 18. Then, the contact hole 22 is filled with a conductive plug 24, and a pad conductive layer 26 contacting the top surface of the conductive plug 24 is formed on the interlayer insulating layer 18. More specifically, the pad conductive layer 26 is formed over the data line 20.
In addition, the MTJ layer S is formed on an area of the pad conductive layer 26 corresponding to the data line 20. A second interlayer insulating layer 28 covering the pad conductive layer 26 and the MTJ layer S is formed on the first interlayer insulating layer 18. A via hole 30 exposing an upper layer of the MTJ layer S is formed in the second interlayer insulating layer 28. A bit line 32 filling the via hole 30 is formed on the second interlayer insulating layer 28 in a direction vertical to the gate electrode and the data line 20.
The MTJ layer S included in the MRAM of FIG. 1 is formed as shown in FIGS. 2 and 3.
As shown in FIG. 2, a lower magnetic layer S1, a tunneling barrier layer S2, and an upper magnetic layer S3 are sequentially formed on a predetermined area of the pad conductive layer 26. Then, a mask pattern M, limiting an area in which the MTJ layer S will be formed, is formed on the upper magnetic layer S3.
The tunneling barrier layer S2 is formed by depositing a metal layer, such as an aluminum Al layer, on the lower magnetic layer S1 and oxidizing the metal layer. In order to oxidize the metal layer, plasma oxidation, UV oxidation, natural oxidation, or ozone oxidation may be used.
Thereafter, as shown in FIG. 3, the MTJ layers are completely formed on the pad conductive layer 26 by etching the above sequentially formed material layers in a reverse order to an order in which they were disposed using the mask pattern M as an etching mask. Thereafter, the mask pattern M is removed. Ion milling using an argon gas, dry etching using a chlorine gas, or reactive ion etching may be used for etching the sequentially formed material layers in the reverse order. In addition, the MTJ layer S may be formed by a lift-off method. Generally, the tunneling barrier layer S2 of the MRAM should be formed uniformly without defects for tunneling to be spin-dependent.
As described above, in the conventional method of forming an MRAM, the tunneling barrier layer S2 is formed by oxidizing a metal layer using plasma oxidation, UV oxidation, natural oxidation, or ozone oxidation. However, some problems may arise due to the oxidation process of the metal layer.
In particular, when the metal layer is oxidized using the plasma oxidation method, an interface of thin layers including the lower magnetic layer S1, which is located under the metal layer, may be damaged. As a result, a magnetic resistance (MR) ratio of the MTJ layer S and/or the stability of the MRAM may be decreased.
Moreover, when the metal layer is oxidized using methods other than the plasma oxidation method, a thickness uniformity of the tunneling barrier layer S2 may be changed. A change in the thickness uniformity of the tunneling barrier layer S2 along with a change in a thickness uniformity of the metal layer, which is inevitable due to the manufacturing process, may dramatically alter characteristics such as the MR ratio of the MRAM.
One solution to the above problems is to form the MTJ layer S of the MRAM using an atomic layer deposition (ALD) method. In a case where the MTJ layer S of the MRAM is formed by an ALD method, a target material layer, i.e., the tunneling barrier layer S2, may be formed to have a uniform thickness. However, since characteristics of the interface of the target material layer and a material layer placed under the target material layer are altered, the MR ratio of the MRAM is decreased.